DPGA utilization and application
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs
IEEE Transactions on Computers
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper describes the architecture of a reconfigurable Complex Programmable Logic Device (CPLD) designed for structured ASIC technology. The proposed architecture adds the feature of reconfiguration to structured ASIC with both static and dynamic reconfiguration options. Static reconfiguration is realized using the possibility to reprogram the SRAM based look-up tables at power-up while dynamic reconfiguration uses embedded memory to implement a multi-context device. Dynamic reconfiguration is realized by storing sixteen CPLD configurations in on-chip memory. This inactive on-chip memory is distributed around the chip allowing single cycle configuration change and it can be accessed either from offchip or from internal logic. Implementation results on structured ASIC validated the solution from both area and timing perspective.