Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Utilizing Multidimensional Loop Parallelism on Large Scale Parallel Processor Systems
IEEE Transactions on Computers
Dynamic Processor Self-Scheduling for General Parallel Nested Loops
IEEE Transactions on Computers
IEEE Transactions on Computers
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Re-configurable computing in wireless
Proceedings of the 38th annual Design Automation Conference
Parallelizing DSP nested loops on reconfigurable architectures using data context switching
Proceedings of the 38th annual Design Automation Conference
The Garp Architecture and C Compiler
Computer
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Fast and Guaranteed C Compilation onto the PACT-XPP" Reconfigurable Computing Platform
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Algorithms and Structures for Reconfigurable Multiplication Units
SBCCI '98 Proceedings of the 11th Brazilian Symposium on Integrated circuit design
Efficient Place and Route for Pipeline Reconfigurable Architectures
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
High-Speed Parallel-Prefix VLSI Ling Adders
IEEE Transactions on Computers
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
IEEE Transactions on Computers
PipeRoute: a pipelining-aware router for reconfigurable architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
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In this paper, we present a new coarse-grained reconfigurable architecture called FleXilicon for multimedia and wireless communications, which improves resource utilization and achieves a high degree of loop level parallelism (LLP). The proposed architecture mitigates major shortcomings with existing architectures through wider memory bandwidth, reconfigurable controller, and flexible word-length support. VLSI implementation of FleXilicon indicates that the proposed pipeline architecture can achieve a high speed operation up to 1 GHz using 65-nm SOI CMOS process with moderate silicon area. To estimate the performance of FleXilicon, we modeled the processor in SystemC and implemented five different types of applications commonly used in wireless communications and multimedia applications and compared its performance with an ARM processor and a TI digital signal processor. The simulation results indicate that FleXilicon reduces the number of clock cycles and increases the speed for all five applications. The reduction and speedup ratios are as large as two orders of magnitude for some applications.