Low power reconfiguration technique for coarse-grained reconfigurable architecture

Authors:
Yoonjin Kim;Rabi N. Mahapatra;Ilhyun Park;Kiyoung Choi
Affiliations:
Department of Computer Science, Texas A&M University, College Station, TX;Department of Computer Science, Texas A&M University, College Station, TX;Samsung Advanced Institute of Technology, Gyeonggi, Korea;School of Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

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Abstract

Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of intellectual property (IP) cores. Reducing power is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, we propose a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration. It shows that the power reduction can be achieved by using the characteristics of loop pipelining, which is a multiple instruction stream, multiple data stream (MIMD)-style execution model. RCP efficiently reduces power consumption in configuration cache without performance degradation. Experimental results show that the proposed approach saves much power even with reduced configuration cache size. Power reduction ratio in the configuration cache and the entire architecture are up to 86.33% and 37.19%, respectively, compared to the base architecture.