A HW/SW partitioning algorithm for dynamically reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Efficient search space exploration for HW-SW partitioning
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 42nd annual Design Automation Conference
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Hardware and software partitioning and reconfiguration cost minimization are two major design challenges for the performance improvement of data-intensive streaming applications by hardware and software co-design approach. In this paper a novel partitioning and scheduling algorithm is proposed for a hybrid system of a microprocessor and a reconfigurable hardware with resource constraint to optimize between hardware resource usage and execution time of an application. We balance the exploitation of spatial parallelism and temporal parallelism in streaming applications by considering the reconfiguration cost vs. the data transfer cost. As the reconfiguration cost is configuration bits size plus the configuration time we try to keep it minimum by exploiting the temporal parallelism maximally.