IEEE Transactions on Computers
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Compilation Approach for Coarse-Grained Reconfigurable Architectures
IEEE Design & Test
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study
Proceedings of the conference on Design, automation and test in Europe - Volume 2
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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This paper presents a compiler methodology for memoryaware mapping on 2-Dimensional coarse-grained reconfigurable architectures that aims in improving the mapped applications' performance. By exploiting data reuse opportunities, the methodology tries to overcome the data memory bandwidth bottleneck, which negatively influences the applications' performance. This is achieved by using foreground memory in the architecture and by properly placing operations in the processing elements. The methodology considers a realistic 2-Dimensional coarse-grained reconfigurable architecture template, which can model the majority of the existing coarse-grained architectures. The experimental results show that the execution time and memory accesses are reduced.