Exploiting the distributed foreground memory in coarse grain reconfigurable arrays for reducing the memory bottleneck in DSP applications

Authors:
Gregory Dimitroulakos;Michalis D. Galanis;Costas E. Goutis
Affiliations:
VLSI Design Laboratory, Electrical & Computer Engineering Department, University of Patras, Greece;VLSI Design Laboratory, Electrical & Computer Engineering Department, University of Patras, Greece;VLSI Design Laboratory, Electrical & Computer Engineering Department, University of Patras, Greece
Venue:
SSIP'05 Proceedings of the 5th WSEAS international conference on Signal, speech and image processing
Year:
2005

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Abstract

This paper presents a methodology for memory-aware mapping on 2-Dimensional coarse-grained reconfigurable architectures that aims in the minimization of the data memory accesses for DSP and multimedia applications. Additionally, the realistic 2-Dimensional coarse-grained reconfigurable architecture template to which the mapping methodology targets, models a large number of existing coarse-grained architectures. This is exploited for quantifiyng the influnce that the architectural features have on performance improvements achieved by our methodology. A novel mapping algorithm is also proposed that uses a list scheduling technique in which the binding, routing, and scheduling phases are considered together and they are steered by a set of costs. The algorithm transfers the data reuse values in the internal interconnection network instead of being fetched in order to reduce the data transfer burden on the bus network. The experimental results show that memory accesses and execution time are reduced since the mapping methodology efficiently exploits the data reuse opportunities.