Evolving hardware with genetic learning: a first step towards building a Darwin machine
Proceedings of the second international conference on From animals to animats 2 : simulation of adaptive behavior: simulation of adaptive behavior
Evolutionary Robotics: The Biology,Intelligence,and Technology
Evolutionary Robotics: The Biology,Intelligence,and Technology
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
PACT XPP—A Self-Reconfigurable Data Processing Architecture
The Journal of Supercomputing
Evolvable Components: From Theory to Hardware Implementations
Evolvable Components: From Theory to Hardware Implementations
Zippy - A coarse-grained reconfigurable array with support for hardware virtualization
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Rapid Prototyping of Digital Systems: SOPC Edition
Rapid Prototyping of Digital Systems: SOPC Edition
Promises and challenges of evolvable hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
Applying Genetic Parallel Programming to Synthesize Combinational Logic Circuits
IEEE Transactions on Evolutionary Computation
Hardware evolution of a digital circuit using a custom VLSI architecture
Proceedings of the South African Institute for Computer Scientists and Information Technologists Conference
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A System-On-Programmable-Chip (SOPC) is presented: the Virtual-FPGA (V-FPGA). It has been designed to ease the implementation of computer hardware evolution by giving direct access to the configuration bits. The V-FPGA is a second configuration layer residing on top of the hardware FPGA layer. When the V-FPGA is uploaded into the FPGA, the following units are created in the FPGA: an array of programmable logic elements (LE); a programmable Registered Element (RE, programmable flip-flops); a programmable interconnection network (Routing Matrix - RM); a configuration memory (CM) and; a configuration port (CP). Computer hardware evolution can be facilitated, as every configuration bit of the virtual configuration array can be accessed by a soft-core microprocessor such as the Altera Nios II.