Closing the gap between ASIC and custom: an ASIC perspective
Proceedings of the 37th Annual Design Automation Conference
PACT XPP—A Self-Reconfigurable Data Processing Architecture
The Journal of Supercomputing
Fast Parallel FFT on a Reconfigurable Computation Platform
SBAC-PAD '03 Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Parallel FFT Algorithms on Network-on-Chips
ITNG '08 Proceedings of the Fifth International Conference on Information Technology: New Generations
Journal of Systems Architecture: the EUROMICRO Journal
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Mapping of the FFT on a reconfigurable architecture targeted to SDR applications
SOC'09 Proceedings of the 11th international conference on System-on-chip
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This paper describes two general-purpose architectures targeted to Field Programmable Gate Array FPGA implementation. The first architecture is based on the coupling of a coarse-grain reconfigurable array with a general-purpose processor core. The second architecture is a homogeneous multi-processor system-on-chip MP-SoC. Both architectures have been mapped onto two different Altera FPGA devices, a StratixII and a StratixIV. Although mapping onto the StratixIV results in higher operating frequencies, the capabilities of the device are not fully exploited. The implementation of a FFT on the two platforms shows a considerable speed-up in comparison with a single-processor reference architecture. The speed-up is higher in the reconfigurable solution but the MP-SoC provides an easier programming interface that is completely based on C language. The authors' approach proves that implementing a programmable architecture on FPGA and then programming it using a high-level software language is a viable alternative to designing a dedicated hardware block with a hardware description language HDL and mapping it on FPGA.