MORA: a new coarse-grain reconfigurable array for high throughput multimedia processing

Authors:
Marco Lanuzza;Stefania Perri;Pasquale Corsonello
Affiliations:
Department of Electronics, Computer Science and Systems, University of Calabria, Rende, CS, Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Rende, CS, Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Rende, CS, Italy
Venue:
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Year:
2007

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Abstract

This paper presents a new coarse-grain reconfigurable array optimized for multimedia processing. The system has been designed to provide a dense support for arithmetic operations, wide internal data bandwidth and efficiently distributed memory resources. All these characteristics are combined into a cohesive structure that efficiently supports a block-level pipelined dataflow, which is particularly suitable for stream oriented applications. Moreover, the new reconfigurable architecture is highly flexible and easily scalable. Thanks to all these features, the proposed architecture can be drastically more speed- and area-efficient than a state of the art FPGA in executing multimedia oriented applications.