Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing

Authors:
Marco Lanuzza;Stefania Perri;Pasquale Corsonello;Martin Margala
Affiliations:
Department of Electronics, Computer Science and Systems, University of Calabria, Rende (CS), Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Rende (CS), Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Rende (CS), Italy;Department of Electrical and Computer Engineering, University of Massachusetts, Lowell, USA
Venue:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Year:
2009

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Abstract

In this paper, the architecture of a novel reconfigurable array, optimized for high-throughput and low-power Digital Signal Processing, is described. The proposed reconfigurable system consists of 2D array of homogeneous coarse-grain reconfigurable cells organized into a hierarchical two-level architecture. The system has been characterized for performing different DSP tasks. Comparison results demonstrate speedups up to 8X with energy efficiency improvement up to 58% over a state of the art FPGA.