Configuration prefetch for single context reconfigurable coprocessors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
MorphoSys: case study of a reconfigurable computing system targeting multimedia applications
Proceedings of the 37th Annual Design Automation Conference
Optimal FPGA module placement with temporal precedence constraints
Proceedings of the conference on Design, automation and test in Europe
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Algorithmic transformation techniques for efficient exploration of alternative application instances
Proceedings of the tenth international symposium on Hardware/software codesign
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Proceedings of the tenth international symposium on Hardware/software codesign
Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Unified theory of real-time task scheduling and dynamic voltage/frequency scaling on MPSoCs
Proceedings of the International Conference on Computer-Aided Design
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Partial dynamic reconfiguration (often referred to as partial RTR) enables true on-demand computing. A dynamically invoked application is assigned resources such as data bandwidth, configurable logic, and the limited logic resources are customized during application execution with partial RTR. In this work, we present key theoretical principles for maximizing application performance when available bandwidth is limited. We exploit bandwidth very effectively by selecting a suitable clock frequency for each task and maximize performance with partial RTR by exploiting data-parallelism property of common image-processing tasks. Our theoretical principles are integrated in our scheduling strategy, SCHEDRTR. We present detailed application case studies on a cycle-accurate simulation platform that addresses micro architectural concerns and includes detailed resource considerations of the Virtex XC2V3000 device. Our results demonstrate that applying SCHEDRTR to common image-filtering applications leads to 15--20% performance gain in scenarios with limited bandwidth, when compared to a sophisticated RTR scheduling strategy with data-parallelism but simpler bandwidth considerations.