A partial reconfigurable architecture for controllers based on Petri nets

Authors:
Paulo Sérgio B. Nascimento;Paulo Romero M. Maciel;Manoel E. Lima;Remy E. Sant'ana;Abel Guilhermino S. Filho
Affiliations:
Federal University of Pernambuco, Recife-PE, Brazil;Federal University of Pernambuco, Recife-PE, Brazil;Federal University of Pernambuco, Recife-PE, Brazil;Federal University of Pernambuco, Recife-PE, Brazil;Federal University of Pernambuco, Recife-PE, Brazil
Venue:
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Year:
2004

Citing 2
Cited 1

Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs

IEEE Transactions on Computers
Hardware Design and Petri Nets

Hardware Design and Petri Nets

Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives

Journal of Systems Architecture: the EUROMICRO Journal

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Abstract

Digital Control System in the industry has been used in most of the applications based on expensive Programmable Logical Controllers (PLC). These Systems are, in general, highly complex and slow, with an operation cycle around 10ms. In this work, a Reconfigurable Logic Controller (RLC) approach is presented, based on a small and low cost Xilinx Virtex-II FPGA architecture, operating as a virtual hardware machine. In this context, the main process is specified in a formal language, based on Petri nets or SFC (Sequential Function Chart). For applications that demand more hardware than that available in the FPGA, a partial reconfiguration mechanism takes place. From the Petri net specification, the main process is split into multiple contexts, which are sequentially executed within the same FPGA, without violating the operation cycle of application.