Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
Proceedings of the 42nd annual Design Automation Conference
Vdd programmability to reduce FPGA interconnect power
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Robust extraction of spatial correlation
Proceedings of the 2006 international symposium on Physical design
FPGA device and architecture evaluation considering process variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing using incremental parameterized statistical timing analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Proceedings of the 43rd annual Design Automation Conference
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction
Proceedings of the 2006 international symposium on Low power electronics and design
Accounting for non-linear dependence using function driven component analysis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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Field programmable dual- Vdd interconnects are effective to reduce FPGA power. However, the deterministic Vdd assignment leverages timing slack exhaustively and significantly increases the number of near-critical paths, which results in a degraded timing yield with process variation. In this paper, we present two statistical Vdd assignment algorithms. The first greedy algorithm is based on sensitivity while the second one is based on timing slack budgeting. Both minimize chip-level interconnect power without degrading timing yield. Evaluated with MCNC circuits, the statistical algorithms reduce interconnect power by 40% compared to the single- Vdd FPGA with power gating. In contrast, the deterministic algorithm reduces interconnect power by 51% but degrades timing yield from 97.7% to 87.5%.