Optimizations for a highly cost-efficient programmable logic architecture

Authors:
Kerry Veenstra;Bruce Pedersen;Jay Schleicher;Chiakang Sung
Affiliations:
Altera Corporation, 101 Innovation Drive, San Jose, CA;Altera Corporation, 101 Innovation Drive, San Jose, CA;Altera Corporation, 101 Innovation Drive, San Jose, CA;Altera Corporation, 101 Innovation Drive, San Jose, CA
Venue:
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Year:
1998

Citing 1
Cited 3

A linear-time heuristic for improving network partitions

25 years of DAC Papers on Twenty-five years of electronic design automation

Interconnect enhancements for a high-speed PLD architecture

FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
The stratixπ routing and logic architecture

FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
The Stratix II logic and routing architecture

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays

Quantified Score

Hi-index	0.00

Visualization

Abstract

Architects of programmable logic devices (PLDs) face several challenges when optimizing a new device family for low manufacturing cost. When given an aggressive die-size goal, functional blocks that seem otherwise insignificant become targets for area reduction. Once low die cost is achieved, it is seen that testing and packaging costs must be considered. Interactions among these three cost contributors pose trade-offs that prevent independent optimization. This paper discusses solutions discovered by the architects optimizing the Altera FLEX 6000 architecture.