Gradient-based optimization of custom circuits using a static-timing formulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Switch-level delay models for digital MOS VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
The Stratix II logic and routing architecture
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Enhancing the area efficiency of FPGAs with hard circuits using shadow clusters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploring area and delay tradeoffs in FPGAs with architecture and automated transistor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
The VTR project: architecture and CAD for FPGAs from verilog to routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and routing architectures are considered. For such explorations, it is not feasible to spend significant amounts of time on transistor-level design. This paper presents an automated transistor sizing tool for FPGA architecture exploration that uses a two-phased approach - a coarse rapid phase with simple modeling followed by refinement with much more accurate models. The output of the system is a design optimized towards a specific area-delay criterion. We compare the quality of our results to prior manual and partially automated approaches. Also, our tool has been used to produce hundreds of candidate architectures which we are releasing to support future high quality explorations.