A novel minloop SB design to improve FPGA routability

Authors:
JIanDe Yu;JinMei Lai
Affiliations:
Fudan University, Shanghai, China;Fudan University, Shanghai, China
Venue:
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Year:
2009

Citing 8
Cited 0

Universal switch modules for FPGA design

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Architecture and CAD for Deep-Submicron FPGAs

Architecture and CAD for Deep-Submicron FPGAs
Introduction to Algorithms

Introduction to Algorithms
Analytical Framework for Switch Block Design

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Crosstalk noise in FPGAs

Proceedings of the 40th annual Design Automation Conference
Architectures and algorithms for field-programmable gate arrays with embedded memory

Architectures and algorithms for field-programmable gate arrays with embedded memory
The Stratix II logic and routing architecture

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing Resources

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we present a new design of a switch box of an FPGA that requires less channel width than conventional designs in routing the same circuit. The design, called a Minloop switch box, is based on the method of minimum-loop-size maximization in routing resources. Experimental results show that the Minloop switch box requires 17.7%, 8.0% and 2.4% less channel width than the classic fabric of Disjoint, Universal and Wilton switch boxes, respectively.