Torc: towards an open-source tool flow

Authors:
Neil Steiner;Aaron Wood;Hamid Shojaei;Jacob Couch;Peter Athanas;Matthew French
Affiliations:
University of Southern California, Arlington, VA, USA;University of Southern California, Arlington, VA, and University of Washington, Seattle, WA, USA;University of Southern California, Arlington, VA and University of Wisconsin-Madison, Madison, WI, USA;Virginia Tech, Blacksburg, VA, USA;Virginia Tech, Blacksburg, VA, USA;University of Southern California, Arlington, VA, USA
Venue:
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Year:
2011

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Abstract

We present and describe Torc - (Tools for Open Reconfigurable Computing) - an open-source infrastructure and tool set, provided entirely as C++ source code and available at http://torc.isi.edu. Torc is suitable for custom research applications, for CAD tool development, and for architecture exploration. The Torc infrastructure can (1) read, write, and manipulate generic netlists - currently EDIF, (2) read, write, and manipulate physical netlists - currently XDL, and indirectly NCD, (3) provide exhaustive wiring and logic information for commercial devices, and (4) read, write, and manipulate bitstream packets (but not configuration frame contents). Torc furthermore provides routing and unpacking tools for full or partial designs, soon to be augmented with BLIF support, and with packing and placing tools. The architectural data for Xilinx devices is generated from non-proprietary XDLRC files, and currently supports 140 devices in 11 families: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex4, Virtex5, Virtex6, Virtex6L, Spartan3E, Spartan6, and Spartan6L. We believe that Altera architectures and designs could be similarly supported if the necessary data were available, and we have successfully used Torc internally with custom architectures.