The Stratix II logic and routing architecture
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations
IEEE Transactions on Computers
Design and Implementation of a Radix-4 Complex Division Unit with Prescaling
ASAP '09 Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors
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Complex reciprocal and square-root operations are used in many digital signal processing (DSP) and numerical computations. In particular, high-throughput fixed-point implementations are desired in high-performance systems. This brief describes a novel design of high-throughput 16-bit fixed-point complex reciprocal/square-root unit. Our approach uses an interpolation algorithm based on the 2-D cubic convolution. Consisting of lookup tables, a small amount of logic, and embedded DSP blocks, the unit is implemented as a four-stage pipeline, achieving a throughput rate of 46 MHz on the Altera Stratix-II FPGA, comparing favorably with the existing designs which achieve a maximum throughput of about 10 MHz on mainstream field-programmable gate arrays (FPGAs). The proposed scheme is also applicable to high-throughput implementation on other platforms as well as of other complex functions.