On metrics for comparing interconnect estimation methods for FPGAs

Authors:
Parivallal Kannan;Shankar Balachandran;Dinesh Bhatia
Affiliations:
Center for Integrated Circuits and Systems, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, Richardson, TX;Center for Integrated Circuits and Systems, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, Richardson, TX;Center for Integrated Circuits and Systems, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas, Richardson, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

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Abstract

Interconnect management is a critical design issue for large field-programmable gate arrays (FPGA) based designs. One of the most important issues for planning interconnection is the ability to reliably and efficiently predict the interconnect requirements of a given design on a given FPGA architecture. Many interconnect estimation methods have been reported so far and the estimation problem is also under active research. From a CAD tool deployment point of view, comparing these estimation methods is very difficult because of the different reporting methods used by the authors. We make an argument for and propose a new uniform reporting metric, based on comparing the estimates with the results of an actual detailed router on both local and global levels. We then compare some of the well known and promising interconnect estimation methods using our new metric on a large number of benchmark circuits.