PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
A fast routability-driven router for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
MPI: The Complete Reference
Parallel Global Routing Algorithms for Standard Cells
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Acceleration of an FPGA router
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Graph based analysis of 2-D FPGA routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Distributed-memory parallel routing for field-programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
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This paper proposes a distributed-memory parallel routing algorithm for FPGAs based on the partitioning of the routing graph under special FPGA architectural constraints. Coarse-grain parallelism is adopted by assigning different processors to the routing of nets within different partitions of the routing graph. The experimental results have demonstrated that TDR can achieve linear and superlinear speedups in relation to the state-of-art VPR router even when it is running on an Ethernet cluster of workstations. However, it usually requires more tracks than VPR for routing the same circuit.