Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Fitting formal methods into the design cycle
DAC '94 Proceedings of the 31st annual Design Automation Conference
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A new symbolic technique for control-dependent scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
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Formally verifying properties of signals in a circuit hasseveral applications in an equivalence checking based formalverification flow.In a hierarchical design, functionalityis divided across blocks.This necessitates the useof constraints on input signals of a block to avoid falsenegatives.Validating such input constraints requires assertionchecking at the outputs of modules generatingthe constrained signals.In this paper, we present anefficient assertion checker for combinational propertieswhich avoids the BDD explosion problem by finding anoptimal intermediate correlation free frontier.It hasbeen successfully used in an industrial setting to uncovera number of bugs.