Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Novel verification framework combining structural and OBDD methods in a synthesis environment
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Efficient Model Checking by Automated Ordering of Transition Relation Partitions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
DAG-aware circuit compression for formal verification
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Kauffman networks: analysis and applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Natural Computing: an international journal
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For decades, the size of silicon CMOS transistors has decreased steadily while their performance has improved. As the devices approach their physical limits, the need for alternative materials, structures and computational schemes becomes evident. This paper considers a computational scheme based on an abstract model of the gene regulatory network called Random Boolean Network (RBN). On one hand, our interest in RBNs is due to their attractive fault-tolerant features. The parameters of an RBN can be tuned so that it exhibits a robust behavior in which minimal changes in network's connections, values of state variables, or associated functions, typically cause no variation in the network's dynamics. On the other hand, a computational scheme based on RBNs seems appealing for emerging technologies in which it is difficult to control the growth direction or precise alignment, e.g. carbon nanotubes.