A theory of diagnosis from first principles
Artificial Intelligence
Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The consistency-based approach to automated diagnosis of devices
Principles of knowledge representation
Using Multiple Models for Debugging VHDL Designs
Proceedings of the 14th International conference on Industrial and engineering applications of artificial intelligence and expert systems: engineering of intelligent systems
Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Fast Error Diagnosis for Combinational Verification
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
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In this paper, we propose a method to detect and correct design faults in a combinational boolean network, based on the modelbased inference. We focus on the design verification for the network with multiple inverter errors. The complexity of this problem is NP-hard and it is harder than the usual verification to find a tractable algorithm. We present an effective algorithm which consists of the generation of the logical formula and its comparison to the specification for each cone in gate implementation. In this algorithm, the heuristic search method is incorporated to avoid the unnecessary backtracking based on the property that a part of the logical formula of each cone must be subformulas of functional specifications if the gate implementation is correct and irredundant.