Extracting Exact Time Bounds from Logical Proofs

Authors:
Mauro Ferrari;Camillo Fiorentini;Mario Ornaghi
Affiliations:
-;-;-
Venue:
LOPSTR '01 Selected papers from the 11th International Workshop on Logic Based Program Synthesis and Transformation
Year:
2001

Citing 5
Cited 3

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Abstract

Accurate evaluation of delays of combinatorial circuits is crucial in circuit verification and design. In this paper we present a logical approach to timing analysis which allows us to compute exact stabilization bounds while proving the correctness of the boolean behavior.