An efficient combinationality check technique for the synthesis of cyclic combinational circuits

  • Authors:

  • Vineet Agarwal;Navneeth Kankani;Ravishankar Rao;Sarvesh Bhardwaj;Janet Wang

  • Affiliations:

  • The University of Arizona, Tucson, AZ;The University of Arizona, Tucson, AZ;The University of Arizona, Tucson, AZ;The University of Arizona, Tucson, AZ;The University of Arizona, Tucson, AZ

  • Venue:
  • Proceedings of the 2005 Asia and South Pacific Design Automation Conference
  • Year:
  • 2005

Quantified Score

Hi-index 0.00

Visualization

Abstract

It has been recently pointed out that cyclic circuits are not necessarily sequential, and cyclic topologies that are combinational generally have lower literal counts than their acyclic counterparts. However, the synthesis of cyclic combinational circuits is potentially expensive due to the need to explore a wide range of cyclic topologies and check each of them for combinationality. We first obtain the acyclic implementation of the given set of boolean functions. Then using a branch-and-bound heuristic, we generate cyclic circuits that are to be checked for combinationality. Unlike earlier complex methods for combinationality check, our approach is to check whether this cyclic circuit is functionally equivalent to the acyclic circuit obtained earlier. While synthesizing cyclic circuits with the proposed method, we observed up to 45%. improvements in the literal count (for Espresso and LGsynth93 benchmarks) over the acyclic circuit synthesized by the Berkeley sis package.