Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
Introduction to Simulation: Programming Techniques and Methods Analysis
Introduction to Simulation: Programming Techniques and Methods Analysis
The synthesis of cyclic combinational circuits
Proceedings of the 40th annual Design Automation Conference
Constructive Analysis of Cyclic Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Efficient Combinational Loops Handling for Cycle Precise Simulation of System on a Chip
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Acyclic modeling of combinational loops
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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This paper presents an efficient algorithm for post-synthesis logic simulation of digital circuits with oscillatory combinational loops. Oscillatory combinational loops can significantly degrade the performance of cycle accurate logic simulators. We provide an algorithm that first, dynamically detects oscillatory loops. Then, we introduce a novel approach to compute a multiple of their oscillation period which is used to optimize the efficiency of the simulation by reducing the number of time points that need to be evaluated. Finally, we provide the experimental results of our optimized algorithm measured on a cycle accurate simulator used in conjunction with a hardware emulator.