A Tool Box to Map System Level Communications on HW/SW Architectures
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
A New Optimized Implemention of the SystemC Engine Using Acyclic Scheduling
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Acyclic modeling of combinational loops
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient simulation of oscillatory combinational loops
Proceedings of the 47th Design Automation Conference
Practical design space exploration of an h264 decoder for handheld devices using a virtual platform
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Proceedings of the 50th Annual Design Automation Conference
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As system integration becomes a reality, the need for efficient, Core based, simulators is pressing. Different levels of simulation accuracy/fidelity are necessary during system design. Naturally, a system is defined as a set of communicating Finite State Machines. In this work, we present a cycle precise simulator that is able to efficiently handle combinational loops existing between the FSMs. We devise a strategy that ensures that the blocks that do not belong to a combinational loop will be evaluated only once per cycle, and that the order of the components within a loop tends to minimize the number of iterations required to achieve stability. We express the problem in a graph theoretic manner, and propose a set of steps to obtain a valid schedule.