Formal specification in VHDL for hardware verification
Proceedings of the conference on Design, automation and test in Europe
Improving Automata Generation for Linear Temporal Logic by Considering the Automaton Hierarchy
LPAR '01 Proceedings of the Artificial Intelligence on Logic for Programming
Model Checking on Product Structures
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
A HOL Conversion for Translating Linear Time Temporal Logic to omega-Automata
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Yet another Look at the LTL Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Introducing Mutual Exclusion in Esterel
PSI '99 Proceedings of the Third International Andrei Ershov Memorial Conference on Perspectives of System Informatics
From linear time to branching time
ACM Transactions on Computational Logic (TOCL)
Hi-index | 0.00 |