Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Symbolic Model Checking
Simple on-the-fly automatic verification of linear temporal logic
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
Branching vs. Linear Time: Final Showdown
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
RuleBase: Model Checking at IBM
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Verification of Reactive Systems: Formal Methods and Algorithms
Verification of Reactive Systems: Formal Methods and Algorithms
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Temporal logic can be more expressive
SFCS '81 Proceedings of the 22nd Annual Symposium on Foundations of Computer Science
Reasoning about infinite computation paths
SFCS '83 Proceedings of the 24th Annual Symposium on Foundations of Computer Science
Resets vs. aborts in linear temporal logic
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
From PSL to LTL: a formal validation in HOL
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
PSL model checking and run-time verification via testers
FM'06 Proceedings of the 14th international conference on Formal Methods
Observability Checking to Enhance Diagnosis of Real Time Electronic Systems
DS-RT '08 Proceedings of the 2008 12th IEEE/ACM International Symposium on Distributed Simulation and Real-Time Applications
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.00 |
In our previous work, we formally validated the correctness of a translation from a subset of Accellera's Property Specification Language (PSL) to linear temporal logic (LTL) using the HOL theorem prover. We also built an interface from HOL to the SMV model checker based on a formal translation of LTL to ω-automata. In the present paper, we describe how this work has been extended and combined to produce a model checking infrastructure for a significant subset of PSL that works by translating model checking problems to equivalent checks for the existence of fair paths through a Kripke structure specified in higher order logic. This translation is done by theorem proving in HOL, so it is proven to be correct. The existence check is carried out using the interface from HOL to SMV. Moreover, we have applied our infrastructure to implement a tool for validating the soundness of a separate PSL model checker.