Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
On the non-termination of MDGs-based abstract state enumeration
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
A Hierarchical Approach to the Formal Verification of Embedded Systems Using MDGs
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Modeling and formal verification of the Fairisle ATM switch fabric using MDGs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we describe the formal verification of an industrial hardware design from PMC-Sierra, Inc. The design under investigation is a Telecom System Block which processes a portion of the SONET (Synchronous Optical Network) line overhead of a received data stream. We adopted a hierarchical modeling and verification approach which follows the natural design hierarchy. The formal specification and verification have been carried out based on MDGs (Multiway Decision Graphs), a new decision diagram subsuming the traditional binary decision diagrams and allowing abstract data and functions. The verification has been performed using both model checking and equivalence checking. To measure the performance of the MDG based model checker, we also conducted a comparative verification of the same design using Cadence FormalCheck tool.