A Hierarchical Approach to the Formal Verification of Embedded Systems Using MDGs

Authors:
Subhashini Balakrishnan;Sofiène Tahar
Affiliations:
-;-
Venue:
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Year:
1999

Citing 0
Cited 2

Formal Verification of a SONET Telecom System Block

ICFEM '02 Proceedings of the 4th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Hierarchical Verification Using an MDG-HOL Hybrid Tool

CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods

Quantified Score

Hi-index	0.00

Visualization

Abstract

With the increasing emergence of mixed hardware/software systems, it is important to ensure the correctness of such a system formally, particularly for real-time and safety critical applications. We present a hierarchical approach to modeling and formally verifying an embedded system at higher levels of abstraction, using Multiway Decision Graphs (MDGs). We demonstrate our approach on the embedded software for a mouse controller application on a commercial microcontroller (PIC 16C71), using the MDG verification tools. Inconsistencies in the assembly code with respect to the specification, as published in the application notes of the manufacturer, were uncovered through our experiments.