Formal hardware verification methods: a survey
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification with Abstract State Machines Using MDGs
Formal Hardware Verification - Methods and Systems in Comparison
Multiway decision graphs and their applications in automatic formal verification of rtl designs
Multiway decision graphs and their applications in automatic formal verification of rtl designs
Interfacing ASM with the MDG tool
ASM'03 Proceedings of the abstract state machines 10th international conference on Advances in theory and practice
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As an efficient representation of Extended Finite State Machines, Multiway Decision Graphs (MDG) are suitable for automatic hardware verification of Register Transfer Level (RTL) designs. However, in some cases, MDG-based verification suffers from the state explosion problem. Some of cases are caused by the standard order used by MDG to order cross-terms that have the same top-level function symbol. These terms usually label decision nodes and must be ordered. We call this kind of state explosion the standard term ordering problem. A solution based on function renaming and cross-term rewriting is proposed in this paper. Experimental results show that this solution can solve the problem completely and thus increase the range of circuits that can be verified by MDG.