Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Fairisle: an ATM network for the local area
SIGCOMM '91 Proceedings of the conference on Communications architecture & protocols
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Evolving algebras 1993: Lipari guide
Specification and validation methods
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Symbolic Model Checking
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
TAPSOFT '97 Proceedings of the 7th International Joint Conference CAAP/FASE on Theory and Practice of Software Development
Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification with Abstract State Machines Using MDGs
Formal Hardware Verification - Methods and Systems in Comparison
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
A Framework for Translating Models and Specifications
IFM '02 Proceedings of the Third International Conference on Integrated Formal Methods
Abstract State Machines: A Method for High-Level System Design and Analysis
Abstract State Machines: A Method for High-Level System Design and Analysis
Model Checking of a Real ATM Switch
ICCD '98 Proceedings of the International Conference on Computer Design
Multiway decision graphs and their applications in automatic formal verification of rtl designs
Multiway decision graphs and their applications in automatic formal verification of rtl designs
Interfacing ASM with the MDG tool
ASM'03 Proceedings of the abstract state machines 10th international conference on Advances in theory and practice
Modeling and formal verification of the Fairisle ATM switch fabric using MDGs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describing transition systems. MDG provides symbolic representation of transition systems with support of abstract sorts and functions. We implemented a transformation tool that automatically generates MDG models from ASM specifications. Then formal verification techniques provided by the MDG tool, such as model checking or equivalence checking, can be applied on the generated models. We illustrate this work with the case study of an ATM switch controller, in which behavior and structure were specified in ASM and, using our ASM-MDG facility, are successfully verified with the MDG tool.