Practical approaches to the verification of a telecom megacell using FormalCheck
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Model checking of S3C2400X industrial embedded SOC product
Proceedings of the 38th annual Design Automation Conference
Formal Verification of an Industrial System-on-a-Chip
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Formal verification of ASMs using MDGs
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper we present our experience on model checking of an Asynchronous Transfer Mode (ATM) switch using the Verification Interacting with Synthesis (VIS) tool. The switch we considered is in use for real applications in the Cambridge Fairisle network. It is composed of four input/output port controllers and a switch fabric, and contains around 1MB memory, 2KB FIFO buffer and 800 registers (latches). To overcome state space explosion, we adopted several abstraction and reduction techniques to reduce the model, and applied compositional reasoning combined with a novel property division approach. Using the above techniques, we succeeded in verifying the entire switch at different hierarchy levels within reasonable CPU time.