Language emptiness checking using MDGs

Authors:
Fang Wang;Sofiène Tahar
Affiliations:
Concordia University, Montreal, Quebec, Canada;Concordia University, Montreal, Quebec, Canada
Venue:
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Year:
2003

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Abstract

Multiway Decision Graphs (MDGs) are efficient diagrams suitable for the modeling and automatic verification of register transfer level designs. The MDG tools provide a first-order branching time model checking, sequential equivalence checking, and combinational verification. In this paper, we present a new model checking algorithm based on language emptiness checking using MDGs. The proposed procedure makes use of the Wring tool from UC Berkeley to generate the property automaton. Language emptiness is checked on the product of this latter and the design automaton represented in terms of MDGs. Compared with the existing MDG model checking, our algorithm shows superior performance. We also conducted experimental comparison between our tool, VIS from UC Berkeley and Cadence FormalCheck.