Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Testing language containment for &ohgr;-automata using BDDs
Information and Computation
What's between simulation and formal verification? (extended abstract)
DAC '98 Proceedings of the 35th annual Design Automation Conference
Checking that finite state concurrent programs satisfy their linear specification
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Symbolic Model Checking
A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Divide and Compose: SCC Refinement for Language Emptiness
CONCUR '01 Proceedings of the 12th International Conference on Concurrency Theory
Efficient Decision Procedures for Model Checking of Linear Time Logic Properties
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Efficient omega-Regular Language Containment
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Algorithmic Verification of Linear Temporal Logic Specifications
ICALP '98 Proceedings of the 25th International Colloquium on Automata, Languages and Programming
Freedom, Weakness, and Determinism: From Linear-Time to Branching-Time
LICS '98 Proceedings of the 13th Annual IEEE Symposium on Logic in Computer Science
Implicit enumeration of strongly connected components and an application to formal verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compositional SCC Analysis for Language Emptiness
Formal Methods in System Design
GSTE is partitioned model checking
Formal Methods in System Design
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We propose a "Sharp" disjunctive decomposition approach for language emptiness checking which is specifically targeted at "Large" or "Difficult" problems. Based on the SCC (Strongly-Connected Component) quotient graph of the property automaton, our method partitions the entire state space so that each state subspace accepts a subset of the language, the union of which is exactly the language accepted by the original system. The decomposition is "sharp" in that this allows BDD operations on the concrete model to be restricted to small subspaces, and also in the sense that unfair and unreachable parts of the submodules and automaton can be pruned away.We also propose "sharp" guided search algorithms for the traversal of the state subspaces, with its guidance the approximate distance to the fair SCCs.We give experimental data which show that our algorithm outperforms previously published algorithms, especially for harder problems.