Introduction to the ISO specification language LOTOS
Computer Networks and ISDN Systems - Special Issue: Protocol Specification and Testing
Reachability Analysis for Formal Verification of SystemC
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Formal verification of SystemC by automatic hardware/software partitioning
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
Race analysis for SystemC using model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Test coverage for loose timing annotations
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
CADP 2006: a toolbox for the construction and analysis of distributed processes
CAV'07 Proceedings of the 19th international conference on Computer aided verification
A systemC/TLM semantics in PROMELA and its possible applications
Proceedings of the 14th international SPIN conference on Model checking software
Idea: simulation based security requirement verification for transaction level models
ESSoS'11 Proceedings of the Third international conference on Engineering secure software and systems
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SystemC/TLM is a widely used standard for system level descriptions of complex architectures. It is particularly useful for fast simulation, thus allowing early development and testing of the targeted software. In general, formal verification of SystemC/TLM relies on the translation of the complete model into a language accepted by a verification tool. In this paper, we present an approach to the validation of a SystemC/TLM description by translation into LOTOS, reusing as much as possible of the original SystemC/TLM C++ code. To this end, we exploit a feature offered by the formal verification toolbox CADP, namely the import of external C code in a LOTOS model. We report on experiments of our approach on the BDisp, a complex graphical processing unit designed by STMicroelectronics.