A Formal Security Model for Microprocessor Hardware
IEEE Transactions on Software Engineering
An Approach for Modeling and Analysis of Security System Architectures
IEEE Transactions on Knowledge and Data Engineering
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Security as a new dimension in embedded system design
Proceedings of the 41st annual Design Automation Conference
Computer Standards & Interfaces
Formal verification of security specifications with common criteria
Proceedings of the 2007 ACM symposium on Applied computing
A formal approach to system level design: metamodels and unified design environments
MEMOCODE '05 Proceedings of the 2nd ACM/IEEE International Conference on Formal Methods and Models for Co-Design
Verification of an industrial systemC/TLM model using LOTOS and CADP
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
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Verification of security requirements in embedded systems is a crucial task - especially in very dynamic design processes like a hard-ware/software codesign flow. In such a case the system's modules and components are continuously modified and refined until all constraints are met and the system design is in a stable state. A transaction level model can be used for such a design space exploration in this phase. It is essential that security requirements are considered from the very first beginning. In this work we demonstrate a novel approach how to use meta-information in transaction level models to verify the consistent application of security requirements in embedded systems.