Interface timing verification drives system design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Checking and deriving module paths in Verilog cell library descriptions
Proceedings of the Conference on Design, Automation and Test in Europe
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A timing verifier that scales to verify complex sequential circuits, modeled in terms of interacting FSMs, while rejecting false sequential and combinational paths has, so far, not been developed. We present an algorithm for this purpose. The inherently modular nature of interactions among FSMs, allow a highly efficient symbolic simulation verification methodology. Experimental results illustrate this methodology's ability to scale, while providing accurate timing verification results.