Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Table-driven implementation of the exponential function in IEEE floating-point arithmetic
ACM Transactions on Mathematical Software (TOMS)
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Verifying the Accuracy of Polynomial Approximations in HOL
TPHOLs '97 Proceedings of the 10th International Conference on Theorem Proving in Higher Order Logics
Defining the IEEE-854 Floating-Point Standard in PVS
Defining the IEEE-854 Floating-Point Standard in PVS
Interpretation of IEEE-854 Floating-Point Standard and Definition in the HOL System
Interpretation of IEEE-854 Floating-Point Standard and Definition in the HOL System
Improving hardware designs whilst simplifying their proof
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
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The IEEE-754 floating-point standard, used in nearly all floating-point applications, is considered as one of the most important standards. Deep datapath and algorithm complexity have made the verification of such floating-point units a very hard task. Theorem proving, offers a good solution to handle such verification tasks. In this paper, we stress on the design changes performed for the sake of formalizing and verifying the IEEE-754 table-driven exponential function in all abstraction levels of the design flow. While verifying the VHDL code implementation against a high-level abstract specification, we were faced by two main problems: (1) the large abstraction gap between the two models; and (2) the flatness of the VHDL code, making it intractable to model and formally verify. We have therefore proposed a hierarchical methodology to solve such modeling problem, and experimented it on our verification task using the HOL theorem proving environment.