System level verification of video and image processing specifications
ISSS '95 Proceedings of the 8th international symposium on System synthesis
From VHDL to efficient and first-time-right designs: a formal approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal Synthesis at the Algorithmic Level
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
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