Testing The 400-MHz IBM Generation-4 CMOS Chip

Authors:
Thomas G. Foote;Dale E. Hoffman;William V. Huott;Timothy J. Koprowski;Bryan J. Robbins;Mary P. Kusko
Affiliations:
-;-;-;-;-;-
Venue:
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Year:
1997

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Abstract

This paper describes the design-for-testframework of the 400MHz CMOS central processor(CP) used in the fourth generation (G4) of the IBM S/390 âline of servers. It will describe details of modeling logic toachieve correct and effective tests as well as describe thetest sets required to test all portions of the design. Thisincludes built-in self-test, array self-test, weighted randompattern generation, algorithmic pattern generation, andmanual patterns. Tests are used to detect faults, static anddynamic, and to debug/diagnose chip failures characteristicto the function under test. The described tests ensure thehighest reliability for the components within the systemand the same test patterns can be applied frommanufacturing all the way to the system level.