A method for generating weighted random test pattern
IBM Journal of Research and Development
Boundary-scan design principles for efficient LSSD ASIC testing
IBM Journal of Research and Development
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Technology-migratable ASIC library design
IBM Journal of Research and Development
Efficient random testing with global weights
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Contactless Digital Testing of IC Pin Leakage Currents
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ASIC test cost/strategy trade-offs
ITC'94 Proceedings of the 1994 international conference on Test
Design of an efficient weighteld random pattern generation system
ITC'94 Proceedings of the 1994 international conference on Test
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The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBM's high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The tester's design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches.