A method for generating weighted random test pattern
IBM Journal of Research and Development
Boundary-scan design principles for efficient LSSD ASIC testing
IBM Journal of Research and Development
Low-Cost Testing of High-Density Logic Components
IEEE Design & Test
Delay Test: The Next Frontier for LSSD Test Systems
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
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Supplying cost effective testing for large application specific integrated circuits (ASICs) is one of the key challenges facing the semiconductor industry. Projections suggest that it will not be cost effective to continue in the current test direction. ASIC suppliers must be able to offer a flexible, cost-effective set of test solutions that will meet a variety of customer requirements. This paper presents some of the trade-offs used in developing optimal test strategies.