A method for generating weighted random test pattern
IBM Journal of Research and Development
Built-in self-test support in the IBM engineering design system
IBM Journal of Research and Development
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Efficient logic-level timing analysis using constraint-guided critical path search
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 1995 IEEE ASIC conference
One-Pass Redundancy Identification and Removal
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Small Test Generator for Large Designs
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Using ATPG for clock rules checking in complex scan designs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Fastpath: a path-delay test generator for standard scan designs
ITC'94 Proceedings of the 1994 international conference on Test
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Static Property Checking Using ATPG v.s. BDD Techniques
ITC '00 Proceedings of the 2000 IEEE International Test Conference
OPTIMIZING THE FLATTENED TEST-GENERATION MODEL FOR VERY LARGE DESIGNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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There exist many different problems in thedesign automation realm that have no simplesolution. Often a problem requires some kind ofsearch through a potential solution space to see ifone or more examples exist to prove or disprove asupposition. In many of these cases it is possible touse an ATPG engine to perform an examination ofthe search space. This paper describes many of thevarious applications of ATPG used within IBMover the past few decades, along with someindication as to the perceived benefits.