Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A method for generating weighted random test pattern
IBM Journal of Research and Development
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient test-point selection for scan-based BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
MFBIST: A BIST Method for Random Pattern Resistant Circuits
Proceedings of the IEEE International Test Conference on Test and Design Validity
Using BIST Control for Pattern Generation
Proceedings of the IEEE International Test Conference
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
ATS '98 Proceedings of the 7th Asian Test Symposium
Deterministic Pattern Generation for Weighted Random Pattern Testing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
SCOAP: Sandia controllability/observability analysis program
DAC '80 Proceedings of the 17th Design Automation Conference
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
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Two noble scan based BIST architectures, namely parallelfixing and serial fixing BIST, which can be implemented atvery low hardware cost even for random pattern resistant circuitsthat have large number of scan elements, are proposed.Both of the proposed BIST schemes use 3-weight weightedrandom BIST techniques to reduce test sequence lengths byimproving detection probabilities of random pattern resistantfaults. A special ATPG is used to generate suitable test cubesets that lead to BIST circuits that require minimum hardwareoverhead. Experimental results show that the proposed BISTschemes can attain 100% fault coverage for all of benchmarkcircuits with drastically reduced test sequence lengths. Thisreduction in test sequence length is achieved at low hardwarecost even for benchmark circuits that have large number scaninputs.