Weighted pseudorandom hybrid BIST

Authors:
Abhijit Jas;C. V. Krishna;Nur A. Touba
Affiliations:
Intel Corporation, Austin, TX and Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX;Cadence Design Systems Inc., Endicott, NY and Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX;Computer Engineering Research Center, Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

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Abstract

This paper presents a new test data-compression scheme that is a hybrid approach between external testing and built-in self-test (BIST). The proposed approach is based on weighted pseudorandom testing and uses a novel approach for compressing and storing the weight sets. Three levels of compression are used to greatly reduce test costs. Experimental results show that the proposed scheme reduces tester storage requirements and tester bandwidth requirements by orders of magnitude compared to conventional external testing, but requires much less area overhead than a full BIST implementation providing the same fault coverage. No test points or any modifications are made to the function logic. The paper describes the proposed hybrid BIST architecture as well as two different ways of storing the weight sets, which are an integral part of this scheme.