On Using Machine Learning for Logic BIST

On Using Twisted-Ring Counters for Test Set Embedding in BIST

Journal of Electronic Testing: Theory and Applications

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST

Journal of Electronic Testing: Theory and Applications

A Ring Architecture Strategy for BIST Test Pattern Generation

Journal of Electronic Testing: Theory and Applications

Characteristic faults and spectral information for logic BIST

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures

ITC '00 Proceedings of the 2000 IEEE International Test Conference

A BIST Pattern Generator Design for Near-Perfect Fault Coverage

IEEE Transactions on Computers

Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST

IEEE Transactions on Computers

Weighted pseudorandom hybrid BIST

IEEE Transactions on Very Large Scale Integration (VLSI) Systems