Balancing structured and ad-hoc design for test: testing of the PowerPC 603TMmicroprocessor

Authors:
Craig Hunter;E. Kofi Vida-Torku;Johnny LeBlanc
Affiliations:
Motorola Inc., Austin, Texas;International Business Machines Corp., Austin, Texas;International Business Machines Corp., Austin, Texas
Venue:
ITC'94 Proceedings of the 1994 international conference on Test
Year:
1994

Citing 6
Cited 4

A method for generating weighted random test pattern

IBM Journal of Research and Development
Pseudorandom built-in self-test methodology and implementation for the IBM RISC System/6000 processor

IBM Journal of Research and Development
Test generation for VLSI chips with embedded memories

IBM Journal of Research and Development
Implementing 1149.1 on CMOS Microprocessors

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A logic design structure for LSI testability

DAC '77 Proceedings of the 14th Design Automation Conference
Transition Fault Simulation

IEEE Design & Test

Design and implementation of the "G2" PowerPC 603e-embedded microprocessor core

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Designing for scan test of high performance embedded memories

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design-For-Test Methodology for Motorola PowerPCTM Microprocessors

ITC '99 Proceedings of the 1999 IEEE International Test Conference
DFT Advances in Motorola's MPC7400, a PowerPCTM Microprocessor

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

The PowerPC 603 microprocessor is a high performance, low power, and low cost RISC microprocessor which was designed at the Somerset Design Center by a team of Motorola, IBM and Apple engineers. The testability and manufacturability features implemented in the PowerPC 603 microprocessor are presented, as well as the issues involved in reconciling a common test plan for two fabrication facilities with differing expectations.