Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
On computing optimized input probabilities for random tests
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Improved Techniques for Estimating Signal Probabilities
IEEE Transactions on Computers
A method for generating weighted random test pattern
IBM Journal of Research and Development
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Evolutionary algorithms in theory and practice: evolution strategies, evolutionary programming, genetic algorithms
PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Design of an Efficient Weighted-Random-Pattern Generation System
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Deterministic Pattern Generation for Weighted Random Pattern Testing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
OBDD-Based Optimization of Input Probabilities for Weighted Random Pattern Generation
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Evolutionary algorithms for the physical design of VLSI circuits
Advances in evolutionary computing
Evolutionary Optimization in Code-Based Test Compression
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
| Hi-index | 0.00 |
We introduce a two-staged Genetic Algorithm for optimizing weighted random pattern testing in a Built-In-Self-Test (BIST) environment. The first stage includes the OBDD-based optimization of input probabilities with regard to the expected test length. The optimization itself is constrained to discrete weight values which can directly be integrated in a BIST environment. During the second stage, the hardware-design of the actual BIST-structure is optimized. Experimental results are given to demonstrate the quality of our approach.